TAS5830
- Supports multiple output configurations
- 2 × 80W, BTL Mode(4Ω, 26V, THD+N=10%)
- 2 × 65W, BTL Mode(4Ω, 26V, THD+N=1%)
- 2 × 74W, BTL Mode(6Ω, 30V, THD+N=10%)
- 2 × 63W, BTL Mode(6Ω, 30V, THD+N=1%)
- 1 × 151W, PBTL Mode(3Ω, 30V, THD+N=10%)
- 1 × 131W, PBTL Mode(3Ω, 30V, THD+N=1%)
- Flexible audio I/O:
- Supports 32, 44.1, 48, 88.2, 96, 192kHz sample rates
- I2S, LJ, RJ, 4- 16 channels TDM input
- SDOUT for audio monitoring, sub-channel, or echo cancellation
- Supports 3-wire digital audio interface (no MCLK required)
- High-efficiency Class-D modulation
- > 90% power efficiency, 70mΩ RDSon
- Excellent audio performance:
- THD+N ≤ 0.03% at 1 W, 1kHz, PVDD = 12V
- SNR ≥ 110dB (A-weighted), ICN ≤ 40µVrms
- Flexible processing features
- 3-Band advanced DRC + 2 EQs + AGL + 2 EQs
- 15 BQs per channel, level meter
- 96kHz, 192kHz processor sampling
- Mixer, volume, dynamic EQ, output crossbar
- PVDD sensing and Class-H algorithm audio signal tracking
- Rattle suppression, Frequency limiter
- Flexible power supply configurations
- PVDD: 4.5V to 30V
- DVDD and I/O: 1.8V or 3.3V
- Excellent integrated self-protection:
- Over-current error (OCE)
- Cycle-by-cycle current limit supports 4 selectable OC levels
- Over-temperature warning (OTW)
- Over-temperature error (OTE)
- Under and over-voltage lock-out (UVLO/OVLO)
- PVDD voltage drop detection
- Easy system integration
- I2C Software Control (TAS5830 supports both Fast and Fast Plus mode) or Hardware Mode
- Fewer passives required compared to open-loop devices
The TAS5830 is a stereo high-performance, closed-loop Class-D with integrated audio processor and up to 192kHz audio support.
When setting the device into Hardware control mode, TAS5830 supports selecting switching frequency, analog gain, BTL/PBTL mode and cycle by cycle current limit threshold through pin configuration. This mode is designed to eliminate end system software driver integration efforts.
The TAS5830 also provides the DSP features Rattle suppression and Frequency limiter. Rattle suppression reduces the gain of the signal at frequencies that cause rattle through interaction with the speaker enclosure, improving sound quality. The frequency limiter process senses the input level, limits the gain of EQ dynamically and helps SPL without phase change.
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | TAS5830 65W Stereo, Digital Input, High Efficiency Closed-Loop Class-D Amplifier with Class-H Algorithm datasheet | PDF | HTML | 20 May 2025 |
User guide | TAS5827, TAS5828M, and TAS5830 Process Flows | PDF | HTML | 13 Jun 2025 | |
EVM User's guide | TAS5830 Evaluation Module | PDF | HTML | 02 May 2025 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
TAS5830EVM — TAS5830 evaluation module
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | CAD symbols, footprints & 3D models |
---|---|---|
HTSSOP (DAD) | 32 | Ultra Librarian |
Ordering & quality
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