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SN54HC112

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Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset

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Data sheet

SN54HC112

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type CMOS Output type Push-Pull Clock frequency (MHz) 20 Supply current (max) (µA) 80 IOL (max) (mA) -4 IOH (max) (mA) 4 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type CMOS Output type Push-Pull Clock frequency (MHz) 20 Supply current (max) (µA) 80 IOL (max) (mA) -4 IOH (max) (mA) 4 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 CFP (W) 16 69.319 mm² 10.3 x 6.73 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Wide operating voltage range of 2V to 6V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 40µA max ICC
  • Typical tpd = 13ns
  • ±4mA output drive at 5V
  • Low input current of 1µA max
  • Wide operating voltage range of 2V to 6V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 40µA max ICC
  • Typical tpd = 13ns
  • ±4mA output drive at 5V
  • Low input current of 1µA max

The SNx4HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high.

The SNx4HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high.
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* Data sheet SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. I) PDF | HTML 16 Sep 2024

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