This reference design outlines a safe torque off (STO) subsystem for a three-phase inverter with CMOS input isolated IGBT gate drivers. The STO subsystem employs a dual-channel architecture (1oo2) with a hardware fault tolerance of 1 (HFT=1). It is implemented following a de-energize trip concept. When the dual STO inputs (STO_1 and STO_2) go active low, the corresponding power supplies of the primary and secondary side of the six isolated IGBT gate drivers, are cut off through load switches. This removes the possibility to control and energize the motor. The STO reference design (1oo2) has been assessed by TÜV SÜD to be generally suitable for SIL 3 and PL e/Cat. 3.
Features
- Dual-channel STO architecture (1oo2) assessed by TÜV SÜD to be suitable for SIL 3 (IEC 61508) and PL e/Cat. 3 (ISO 13849)
- TÜV report, safety concept description and qualitative system FMEA available to further help designers implement the STO subsystem
- STO subsystem for three-phase inverters with CMOS-input isolated IGBT gate drivers such as ISO5852S, UCC21750 or UCC5350
- 24-V isolated input receivers ISO1211 compliant to IEC 61131-2 and ±60-V input tolerance with reverse polarity protection
- Interface to MCU (SIL 1) for diagnostic coverage of the load switches in the STO subsystems
- Option to monitor input and output supply UVLO of the ISO5852S through RDY pin and additional monitoring capabilities with UCC21750 integrated analog-to-PWM isolated sensor