System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.PSC1		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.PSC1		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.PSC1		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.PSC1
Path C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.4\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.4\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.4\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.4\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.4\ISE_DS\common\bin\nt;
C:\Xilinx\12.4\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\WINDOWS\system32\WindowsPowerShell\v1.0;
C:\Program Files\Altium Designer Summer 09\System;
C:\Program Files\Texas Instruments Fusion Digital Power Designer\bin;
C:\Cadence\SPB_16.3\tools\bin;
C:\Cadence\SPB_16.3\tools\libutil\bin;
C:\Cadence\SPB_16.3\tools\fet\bin;
C:\Cadence\SPB_16.3\tools\pcb\bin;
C:\Cadence\SPB_16.3\tools\specctra\bin;
C:\Cadence\SPB_16.3\tools\PSpice;
C:\Cadence\SPB_16.3\tools\PSpice\Library;
C:\Cadence\SPB_16.3\tools\Capture;
C:\Cadence\SPB_16.3\OpenAccess\bin\win32\opt;
C:\Program Files\MATLAB\R2010b\runtime\win32;
C:\Program Files\MATLAB\R2010b\bin;
C:\Program Files\CVSNT\;
C:\Modeltech_xe_starter\win32xoem		 C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.4\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.4\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.4\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.4\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.4\ISE_DS\common\bin\nt;
C:\Xilinx\12.4\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\WINDOWS\system32\WindowsPowerShell\v1.0;
C:\Program Files\Altium Designer Summer 09\System;
C:\Program Files\Texas Instruments Fusion Digital Power Designer\bin;
C:\Cadence\SPB_16.3\tools\bin;
C:\Cadence\SPB_16.3\tools\libutil\bin;
C:\Cadence\SPB_16.3\tools\fet\bin;
C:\Cadence\SPB_16.3\tools\pcb\bin;
C:\Cadence\SPB_16.3\tools\specctra\bin;
C:\Cadence\SPB_16.3\tools\PSpice;
C:\Cadence\SPB_16.3\tools\PSpice\Library;
C:\Cadence\SPB_16.3\tools\Capture;
C:\Cadence\SPB_16.3\OpenAccess\bin\win32\opt;
C:\Program Files\MATLAB\R2010b\runtime\win32;
C:\Program Files\MATLAB\R2010b\bin;
C:\Program Files\CVSNT\;
C:\Modeltech_xe_starter\win32xoem		 C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.4\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.4\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.4\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.4\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.4\ISE_DS\common\bin\nt;
C:\Xilinx\12.4\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\WINDOWS\system32\WindowsPowerShell\v1.0;
C:\Program Files\Altium Designer Summer 09\System;
C:\Program Files\Texas Instruments Fusion Digital Power Designer\bin;
C:\Cadence\SPB_16.3\tools\bin;
C:\Cadence\SPB_16.3\tools\libutil\bin;
C:\Cadence\SPB_16.3\tools\fet\bin;
C:\Cadence\SPB_16.3\tools\pcb\bin;
C:\Cadence\SPB_16.3\tools\specctra\bin;
C:\Cadence\SPB_16.3\tools\PSpice;
C:\Cadence\SPB_16.3\tools\PSpice\Library;
C:\Cadence\SPB_16.3\tools\Capture;
C:\Cadence\SPB_16.3\OpenAccess\bin\win32\opt;
C:\Program Files\MATLAB\R2010b\runtime\win32;
C:\Program Files\MATLAB\R2010b\bin;
C:\Program Files\CVSNT\;
C:\Modeltech_xe_starter\win32xoem		 C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.4\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.4\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.4\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.4\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.4\ISE_DS\common\bin\nt;
C:\Xilinx\12.4\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\WINDOWS\system32\WindowsPowerShell\v1.0;
C:\Program Files\Altium Designer Summer 09\System;
C:\Program Files\Texas Instruments Fusion Digital Power Designer\bin;
C:\Cadence\SPB_16.3\tools\bin;
C:\Cadence\SPB_16.3\tools\libutil\bin;
C:\Cadence\SPB_16.3\tools\fet\bin;
C:\Cadence\SPB_16.3\tools\pcb\bin;
C:\Cadence\SPB_16.3\tools\specctra\bin;
C:\Cadence\SPB_16.3\tools\PSpice;
C:\Cadence\SPB_16.3\tools\PSpice\Library;
C:\Cadence\SPB_16.3\tools\Capture;
C:\Cadence\SPB_16.3\OpenAccess\bin\win32\opt;
C:\Program Files\MATLAB\R2010b\runtime\win32;
C:\Program Files\MATLAB\R2010b\bin;
C:\Program Files\CVSNT\;
C:\Modeltech_xe_starter\win32xoem
XILINX C:\Xilinx\12.4\ISE_DS\ISE\ C:\Xilinx\12.4\ISE_DS\ISE\ C:\Xilinx\12.4\ISE_DS\ISE\ C:\Xilinx\12.4\ISE_DS\ISE\
XILINX_DSP C:\Xilinx\12.4\ISE_DS\ISE C:\Xilinx\12.4\ISE_DS\ISE C:\Xilinx\12.4\ISE_DS\ISE C:\Xilinx\12.4\ISE_DS\ISE
XILINX_EDK C:\Xilinx\12.4\ISE_DS\EDK C:\Xilinx\12.4\ISE_DS\EDK C:\Xilinx\12.4\ISE_DS\EDK C:\Xilinx\12.4\ISE_DS\EDK
XILINX_PLANAHEAD C:\Xilinx\12.4\ISE_DS\PlanAhead C:\Xilinx\12.4\ISE_DS\PlanAhead C:\Xilinx\12.4\ISE_DS\PlanAhead C:\Xilinx\12.4\ISE_DS\PlanAhead
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   adc12d800_rb.prj  
-ifmt   mixed MIXED
-ofn   adc12d800_rb  
-ofmt   NGC NGC
-p   xc4vlx25-11-ff668  
-top   adc12d800_rb  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-power Power Reduction NO NO
-uc Synthesis Constraints File "C:/fpga/adc12d1x00rb_design_package/ADC12D1x00RB Design Package/FPGA Source Code/src/adc12d1000.xcf"  
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy No NO
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES YES
-sd Cores Search Directories {"../coregen" }  
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-dsp_utilization_ratio DSP Utilization Ratio 100 100%
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   LUT LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   NO NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-use_dsp48   Auto AUTO
-iobuf   YES YES
-max_fanout   500 500
-bufg   32 32
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Auto AUTO
-use_sync_set   Auto AUTO
-use_sync_reset   Auto AUTO
-iob   Auto AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc4vlx25-ff668-11 None
-sd Macro Search Path ../coregen None
-uc   C:/fpga/adc12d1x00rb_design_package/ADC12D1x00RB Design Package/FPGA Source Code/src/adc12d800.ucf None
 
Map Property Settings
Switch Name Property Name Value Default Value
-ol Place & Route Effort Level (Overall) high high
-ir Use RLOC Constraints OFF OFF
-t Starting Placer Cost Table (1-100) Map 1 0
-cm Optimization Strategy (Cover Mode) area area
-intstyle   ise None
-o   adc12d800_rb_map.ncd None
-pr Pack I/O Registers/Latches into IOBs off off
-p   xc4vlx25-ff668-11 None
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-t   1 1
-intstyle   ise  
-ol Place & Route Effort Level (Overall) high std
-w   true false
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM)2 Quad CPU Q9505 @ 2.83GHz/2826 MHz Intel(R) Core(TM)2 Quad CPU Q9505 @ 2.83GHz/2826 MHz Intel(R) Core(TM)2 Quad CPU Q9505 @ 2.83GHz/2826 MHz Intel(R) Core(TM)2 Quad CPU Q9505 @ 2.83GHz/2826 MHz
Host SC-AJOJSC1 SC-AJOJSC1 SC-AJOJSC1 SC-AJOJSC1
OS Name Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional
OS Release Service Pack 3 (build 2600) Service Pack 3 (build 2600) Service Pack 3 (build 2600) Service Pack 3 (build 2600)