SLVSBD1B December   2012  – August 2025 TPS65175

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations
  6. 5 Ordering Information #GUID-A66BA10C-7D19-4133-842F-4CC0C2AD52C6/SLVSAP8211
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Thermal Information
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 I2C Interface Timing Characteristics #GUID-79B32470-0E13-4B06-925C-21E3D7AB5A31/SLVSAE57133
    6. 6.6 I2C Timing Diagrams
    7.     14
    8.     15
    9.     16
    10. 6.7 Typical Characteristics
  8. 7 DAC Range Summary
    1.     19
    2. 7.1 Sequencing
    3. 7.2 Power-Up
    4. 7.3 Power-Down
  9. 8 Detailed Description
    1. 8.1  Boost Converter (VDD)
      1. 8.1.1 Enable Signal (DLY2)
      2. 8.1.2 Boost Converter Operation
      3. 8.1.3 Startup (Boost Converter)
      4. 8.1.4 Protections (Boost Converter)
      5. 8.1.5 Setting the Output Voltage VDD
    2. 8.2  Boost Converter Design Procedure
      1. 8.2.1 Inductor Selection (Boost Converter)
      2. 8.2.2 Rectifier Diode Selection (Boost Converter)
      3. 8.2.3 Compensation (COMP)
      4. 8.2.4 Input Capacitor Selection
      5. 8.2.5 Output Capacitor Selection
      6. 8.2.6 DCM Mode
    3. 8.3  Buck Converter (VCC)
      1. 8.3.1 Enable Signal (UVLO)
      2. 8.3.2 Buck converter Operation
      3. 8.3.3 Startup and Short Circuit Protection (Buck Converter)
      4. 8.3.4 Setting the Output Voltage VCC
    4. 8.4  Buck Converter Design Procedure
      1. 8.4.1 Inductor Selection (Buck Converter)
      2. 8.4.2 Rectifier Diode Selection (Buck Converter)
      3. 8.4.3 Input Capacitor Selection (Buck Converter)
      4. 8.4.4 Output Capacitor Selection (Buck Converter)
      5. 8.4.5 DCM Mode
    5. 8.5  Synchronous Buck Converter (HVDD)
      1. 8.5.1 Enable Signal (DLY2)
      2. 8.5.2 Startup and Short Circuit Protection (Synchronous Buck Converter)
      3. 8.5.3 Setting the output voltage HVDD
    6. 8.6  Synchronous Buck Converter Design Procedure
      1. 8.6.1 Inductor Selection (Synchronous Buck Converter)
      2. 8.6.2 Input Capacitor Selection
      3. 8.6.3 Output Capacitor Selection
    7. 8.7  Positive Charge Pump Controller (VGH) and Temperature Compensation
      1. 8.7.1 Enable Signal (DLY3)
      2. 8.7.2 Positive Charge Pump Controller Operation
    8. 8.8  Positive Charge Pump Design Procedure
      1. 8.8.1 Diodes selection (CPP)
      2. 8.8.2 Capacitors Selection (CPP)
      3. 8.8.3 Selecting the PNP Transistor (CPP)
      4. 8.8.4 Positive Charge Pump Protection
    9. 8.9  VGH Temperature Compensation
      1. 8.9.1 Setting the output voltage VGH_LT and VGH_HT
    10. 8.10 Negative Charge Pump (VGL)
      1. 8.10.1 Enable Signal (DLY1)
      2. 8.10.2 Setting the output voltage VGL
    11. 8.11 Negative Charge Pump Design Procedure
      1. 8.11.1 Diodes Selection (CPN)
      2. 8.11.2 Capacitors selection (CPN)
      3. 8.11.3 Selecting the NPN Transistor (CPN)
      4. 8.11.4 Negative Charge Pump Protection
    12. 8.12 P-Vcom Voltage and Gain (VCOM)
      1. 8.12.1 Enable Signal (DLY2)
    13. 8.13 P-Vcom Design Procedure
      1. 8.13.1 Setting the P-Vcom gain
    14. 8.14 P-Vcom Temperature Compensation
      1. 8.14.1 Setting the VCOM output voltage
    15. 8.15 Gamma Buffer (GMA1-GMA6)
      1. 8.15.1 Enable Signal (DLY2)
      2. 8.15.2 Setting the output voltage of GMA1-GMA6
      3. 8.15.3 Output Load (Gamma Buffer)
    16. 8.16 Level Shifters
    17. 8.17 State Machine
    18. 8.18 GCLK
    19. 8.19 MCLK
    20. 8.20 GST
    21. 8.21 E/O
    22. 8.22 Reverse
    23. 8.23 VGH_F and VGH_R
    24. 8.24 VST
    25. 8.25 RESET
    26. 8.26 EVEN and ODD
    27. 8.27 Abnormal Operation
    28. 8.28 CLK1 to CLK6
    29. 8.29 Gate Voltage Shaping
    30. 8.30 Power Supply Sequencing (CLK1-CLK6, VST, RESET)
    31. 8.31 Power Supply Sequencing (EVEN, ODD)
    32. 8.32 Power Supply Sequencing (VGH_F, VGH_R)
    33.     101
    34. 8.33 Typical Applications
  10. 9 APPENDIX – I2C INTERFACE
    1. 9.1 I2C Serial Interface Description
  11. 10Detailed Description
    1. 10.1 DAC Settings
    2. 10.2 I2C Interface Protocol
    3. 10.3 Temperature Compensation
    4. 10.4 PCB Layout Recommendations
  12. 11Register Map
  13. 12DAC Registers
  14. 13Electrostatic Discharge Caution
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
      1. 15.1.1 Packaging Information
      2. 15.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Data Sheet

Fully Programmable LCD Bias IC for GIP TV
with Integrated 12-Ch Level Shifters and 6-Ch Gamma Buffers